[세미나] Toward Minimum Energy Operation of Voltage-Scaled Circuits

2018-06-29l Hit 6372

Toward Minimum Energy Operation of Voltage-Scaled Circuits

 Prof. Hidetoshi Onodera

  ■ Date: Jul. 6, 2018 (Friday)
  ■ Time: 16:30 – 17:30
  ■ Place: Room 1112, Building 301


  There is a set of supply voltage (Vdd) and threshold voltages (Vthn and Vthp), which is called "Minimum Energy Point (MEP)" that leads to the minimum energy consumption per operation under a specified timing constraint. First, simulated MEP loci in a Vdd-Vth space will be shown for a model circuit and a processor. The shape of the locus suggests us an effective strategy for DVFS and ABB. Then a measured MEP locus of an on-chip memory will be explained together with the standard-cell based structure of the memory for stable operation under a lower supply voltage for reducing energy consumption. Next, an algorithm for MEP tracking will be introduced. MEP operation requires information on operating conditions such as Vth and temperature together with threshold-voltage control capability. Ring-oscillator-based on-chip monitors and a body-bias-generator compatible with cell-based design will be discussed.


  Hidetoshi Onodera received the B.E., M.E., and Dr. Eng. degrees in Electronic Engineering, all from Kyoto University, Kyoto, Japan. He joined the Department of Electronics, Kyoto University, in 1983, and is currently a Professor in the Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. His research interests include design technologies for Digital, Analog, and RF LSIs, with particular emphasis on low-power design, design for manufacturability, and design for dependability.
  Dr. Onodera served as the Program Chair and General Chair of ICCAD and ASPDAC.  He was the Chairman of SSCS Kansai Chapter, IEEE CASS Kansai Chapter, and IEEE Kansai Section, and the Vice President of Awards in IEEE CEDA Executive Committee. He served as the Editor-in-Chief of IEICE Transactions on Electronics and IPSJ Transactions on System LSI Design methodology. He is an IEEE Fellow, an IEICE Fellow, and a Member of Science Council of Japan.

Contact: Prof. Kiyoung Choi (880-6768)