▲ (From left) Prof. Chul-Ho Lee (corresponding author), Ph.D. Yeon Ho Kim (first author), Ph.D. candidate Jaeho Lee (co-author), and integrated M.S.–Ph.D. candidate Donghyun Lee (co-author)

Seoul National University’s College of Engineering announced that the research team led by Professor Chul-Ho Lee of the Department of Electrical and Computer Engineering has comprehensively proposed development directions for “gate stack”*, a core technology in two-dimensional (2D) transistors, which are emerging as next-generation semiconductor devices.

*gate stack: the structure that controls current flow in transistors, consisting of a dielectric and metal stacked on top of the conductive layer

On September 11, the findings were published in Nature Electronics (Impact Factor 40.9), a leading international journal at the forefront of semiconductor technology.

■ Research Background

Modern semiconductors rely predominantly on silicon-based CMOS (Complementary Metal-Oxide-Semiconductor) technology, which has driven improvements in device performance and degree of integration over the past several decades. However, at today’s ultra-fine process scales of just a few nanometers (nm), this approach is encountering physical limitations. As a promising alternative channel material, 2D semiconductors—composed of atomically thin layers yet still capable of maintaining excellent electrical properties—are gaining increasing attention.

Major global semiconductor companies and research institutes—including Samsung, TSMC, Intel, and IMEC—have already incorporated plans into their technology roadmaps to adopt 2D semiconductor transistors as the next-generation alternative to silicon in the mid-2030s, launching large-scale R&D efforts. In this context, 2D semiconductors are no longer a technology of the distant future but are rapidly emerging as the next mainstream driver of the global semiconductor industry.

Yet, one of the greatest obstacles to the commercialization of 2D semiconductors lies in gate stack process technology. The gate stack is a core structure of semiconductors that controls the flow of current, and its quality directly determines the performance and reliability of the device. However, directly applying conventional silicon transistor processes to 2D semiconductors leads to degraded dielectric* quality, interfacial defects, and current leakage. Developing new materials and processes to overcome these issues is considered the most critical challenge for the commercialization of 2D semiconductors.

*dielectric : insulating layer that prevents the flow of electricity

■ Research Achievements

In response, Prof. Chul-Ho Lee’s research team analyzed various gate stack formation methods and quantitatively compared them across key performance metrics, thereby outlining a roadmap for future technological development.

First, the research team classified gate stack formation methods into five categories: △van der Waals (vdW) dielectric, △naturally oxidized dielectric, △crystalline dielectric transfer method (quasi-vdW), △high-κ dielectric formation using a seed layer (vdW-seeded), and △methods compatible with conventional processes (non-vdW-seeded). Each method was then evaluated against key performance metrics—including interface defects, oxide film thickness, leakage current, threshold voltage, and operating voltage—and compared against the targets set by the International Roadmap for Devices and Systems (IRDS). Through this process, the team established a systematic development roadmap that can serve as a reference for both academia and industry.

The research team also highlighted the potential of gate stacks incorporating ferroelectric* materials to be scaled up to next-generation devices. For example, ferroelectric-based gate stacks could enable ultra-low-power logic, non-volatile memory, and in-memory computing. In addition, the team provided concrete guidelines for practical implementation, addressing essential factors such as BEOL (Back-End-of-Line) process compatibility, low-temperature deposition below 400°C, wafer-wide uniformity, and long-term reliability, thereby emphasizing real-world industrial applicability beyond purely theoretical discussions.

*ferroelectric: a material that retains electric polarization even in the absence of an external electric field. It is used in applications such as the implementation of non-volatile memory.

This study is significant in that it quantitatively compared the performance of 2D semiconductor gate stacks across multiple metrics and evaluated them against IRDS targets, thereby providing a blueprint for the development of next-generation semiconductors. In doing so, the researchers not only confirmed the feasibility of implementing ultra-low-power, high-performance transistors but also proposed concrete technological directions considering future 3D monolithic stacking and BEOL-compatible processes, marking an innovative achievement. Furthermore, the technologies presented in this research are expected to serve as core foundational technologies driving the development of next-generation ICT infrastructure, including AI semiconductors, ultra-low-power mobile chips, and ultra-high-density servers.

■ Researchers' Remarks

Prof. Chul-Ho Lee stated, “The biggest obstacle to the commercialization of 2D transistors is the implementation of high-quality gate stacks. This study provides a standard blueprint to overcome that challenge, which has significant academic and industrial implications. Moving forward, we plan to actively expand research on actual device integration and commercialization through industry–academia collaboration.”

■ About the Research Team

Prof. Chul-Ho Lee’s research team at Seoul National University is actively leading the international academic community in the field of 2D semiconductor devices, particularly in high-quality gate stack technology. The team goes beyond purely theoretical proposals, conducting comprehensive research that encompasses actual device fabrication and process integration. By taking the lead in addressing key challenges of next-generation semiconductors, the group has established itself as a central player driving the global trajectory of future semiconductor research.

■ Researcher Career Path

The first author of this paper, Ph.D. Yeon Ho Kim, is currently working as a postdoctoral researcher in the ECE Department at SNU, with a focus on metal-semiconductor contact and gate stack-related research for 2D semiconductor-based transistors. Building on this achievement, he is expected to demonstrate both academic and industrial leadership in the field of next-generation 2D semiconductor integrated devices.

This research was conducted with support from the Next Generation Intelligence Semiconductor Development Program and the Nano and Materials Technology Development Program (Future Technology Laboratory), both funded by the Ministry of Science and ICT. Graduate students involved in the study also received support from BK21 Four and the Graduate School of AI Semiconductor.

Figure 1. Roadmap of CMOS logic technology development and the potential of angstrom-scale 2D transistors

[Reference]

Kim, Y.H., Lee, D., Huh, W. et al. Gate stack engineering of two-dimensional transistors. Nat Electron (2025). https://www.nature.com/articles/s41928-025-01448-5

[Contact]

Ph.D. Yeon Ho Kim, Laboratory of Emerging Electronics & optoElectronics (Lab.EEE), Department of Electrical and Computer Engineering, Seoul National University / julianus95@snu.ac.kr

Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56869

Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr