From left: Professor Jaehyouk Choi, Department of Electrical and Computer Engineering, Seoul National University; doctoral candidates Jeongbeom Seo, Jaeho Kim, and Moonjae Chae Three papers from the Integrated Circuits and Systems Lab (ICSL) led by Professor Jaehyouk Choi, by the research team consisting of Jeongbeom Seo, Yunseo Cho, and Yoohwan Shin, the research team consisting of Jaeho Kim, Myungho Han, and Jooeun Bang, and the reseach team consisting of Moonjae Chae, Sehyun Jang, Chanwoong Hwang, and Hangi Park, have been accepte at the upcoming ISSCC in February 2025. Since its establishment in 1954, the ISSCC, held annually in February in San Francisco, has maintained its status as the largest and most prestigious global conference in the field of integrated circuit design, and is often called the “Olympics of semiconductor design.” Each year, over 4,000 semiconductor design researchers from leading industries, universities, and research institutions worldwide attend the conference, presenting their latest advancements and discussing the future of the semiconductor industry. The three accepted papers from Professor Choi’s team present groundbreaking solutions to technical challenges in next-generation HBM interfaces and in ultra-high-speed wired and wireless communications through innovative circuit design concepts. The details are as follows: Accepted Paper 1. [Memory] A new clock distribution circuit design technology for next-generation HBM that drastically reduces power consumption of clock distribution to below one-tenth of previous levels while enhancing signal integrity. Accepted Paper 2. [Digital Circuits] A novel low-voltage regulator design technology that stabilizes supply voltage at unprecedented speeds to mitigate degradation due to clock jitter caused by sudden supply voltage changes in next-generation HBM. Accepted Paper 3. [RF] An ultra-low-noise fractional frequency synthesizer designed for high-speed wired and wireless communication, which effectively addresses PLL performance degradation issues caused by quantization noise in digital PLLs. Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=55477 Translated by: Dohyung Kim, English Editor of the Department of Electrical and Computer Engineering, kimdohyung@snu.ac.kr...
Oct 16, 2024