A research team from Professor Seong-Cheol Kim’s laboratory in the Department of Electrical and Computer Engineering at Seoul National University—consisting of Jihye Kim, Soram Kim, and Sechan Oh—won the President’s Award from the Institute of Information & Communications Technology Planning & Evaluation (IITP) at “ICT Challenge 2025,” organized by the Ministry of Science and ICT and IITP. ICT Challenge 2025 is a competition in which teams of three master’s or doctoral students participating in one of the following government-supported programs—▲Information Technology Research Center Program, ▲ICT Creative Consilience Program, and ▲Innovative Human Resource Development for Local Intellectualization Program—present and demonstrate practical and creative research ideas in their respective fields of study. Now in its 7th year since its launch in 2019, the competition attracted a record 206 teams (618 participants) from 81 research centers across 38 universities nationwide. Under the theme “Imaginations of Future Talent Become Reality”, participants showcased innovative ideas in various fields, including ▲Artificial Intelligence (AI) and Software (SW), ▲Smart Devices (including AI semiconductors), ▲Digital Convergence, and ▲Cybersecurity. Following preliminary rounds, mentoring sessions with employees from sponsoring companies (Amazon Korea and Kakao), and a final evaluation stage, 16 teams were ultimately selected as award recipients. Prof. Seong-Cheol Kim’s research team won the IITP President’s Award for their project titled “Real-Time Three-Dimensional Mapping and Aerial Monitoring System through UAM Collaboration,” and received a cash price of 5 million KRW. Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=57001 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

▲ Professor Jae-Hyeung Park (corresponding author), Ph.D. candidate Woongseob Han (first author), and integrated M.S.–Ph.D. candidate Chanseul Lee (co-author), Department of Electrical and Computer Engineering, Seoul National University The College of Engineering at Seoul National University announced that a research team led by Professor Jae-Hyeung Park from the ECE Department has developed an occlusion-based holographic augmented reality (AR) display that significantly enhances visual realism in AR environments. By integrating a holographic display with an optical occlusion system, the team achieved a new level of visual fidelity in AR. Furthermore, they implemented opaque three-dimensional virtual imagery and optically generated virtual shadows, reproducing visual effects in which virtual objects interact with real-world environments. Recognizing that visual information in AR environments is typically concentrated around virtual objects rather than distributed across the entire space, the research team also introduced an AI-based hologram generation algorithm optimized for sparse holographic images*. * sparse holographic image: a hologram in which visual data exists only in limited regions of the entire image space On October 7, the findings were published as an Inside Front Cover Article in Laser & Photonics Reviews (IF: 10.0), an internationally renowned journal in the field of optics published by Wiley-VCH based in Germany. ▲ Laser & Photonics Reviews Inside Front Cover ■ Research Background As AR glasses emerge as next-generation smart devices following smartphones, leading global technology companies have been actively investing in their development. Despite rapid progress, however, currently commercialized or publicly unveiled AR glasses remain limited in that they are unable to implement occlusion effects, where virtual images obscure real-world objects. The absence of occlusion—a key visual cue for human depth perception—causes virtual images to appear semi-transparent and unrealistically superimposed on the physical environment. Consequently, the realism of the AR environment and the user’s sense of immersion are significantly diminished. Moreover, existing AR glasses reproduce three-dimensional images solely through binocular disparity while keeping monocular depth cues fixed, resulting in a vergence-accommodation conflict (VAC). The visual fatigue and dizziness experienced by users due to VAC have long been identified as major obstacles to the widespread adoption of near-eye displays, including AR glasses. Previous studies addressing this issue have explored approaches such as adding an occlusion optics module in front of the display to selectively block real-world light and render opaque virtual images, or employing techniques such as holography, light-field displays, and variable-focus technologies to reproduce monocular three-dimensional images. However, efforts to achieve both occlusion effects and three-dimensional imaging simultaneously have largely remained at a preliminary stage, underscoring the need for more in-depth research to enhance the visual realism of AR environments. ■ Research Achievements To address this challenge, Prof. Jae-Hyeung Park’s research team developed a holographic AR display that realizes an AR environment with unprecedented visual realism by combining a holographic AR system—capable of reproducing ideal three-dimensional images—with an optical occlusion system that blocks the real-world background. The research team first noted that the structure of the optical occlusion system is identical to that of a 4f system-based Fourier filter structure*, which is commonly used in holographic displays to eliminate noise information. Accordingly, the team utilized a single Digital Micromirror Device (DMD)* placed within a single 4f system to function as both a Fourier filter and an occlusion mask. By employing a time-multiplexing technique, they enabled both occlusion and noise elimination to be performed within a unified system. * Fourier filter structure : optical configuration that analyzes complex images into their frequency components, allowing selective removal or correction of noise * DMD : reflective optical element composed of numerous microscopic mirrors, used to rapidly control the brightness and pattern of holographic display images Taking a step further, the research team incorporated the dynamic characteristics of the DMD—unlike conventional fixed Fourier filters—into the AI-based hologram generation algorithm. This approach significantly reduced the search space of the optimizer, achieving an average improvement of 11 decibels (dB) in the Peak Signal-to-Noise Ratio (PSNR)* of sparse holographic images compared to conventional algorithms under identical conditions. In addition, by applying a time-multiplexing technique, the team suppressed Speckle noise*—a major factor degrading holographic image quality—and doubled the field of view. * PSNR : a measure of the ratio between the original and reconstructed image signals, used to evaluate image or image reconstruction quality. A higher PSNR value indicates superior image quality. * Speckle noise : a granular interference pattern that appears as fine dotted noise in images The research team also built a benchtop prototype* based on the proposed system, successfully reproducing opaque three-dimensional AR images in which virtual objects occlude the real-world background. Further, the team reproduced AR scenes in which virtual objects cast realistic shadows onto the real world by leveraging the occlusion effect. Experimental results showed a significant increase in contrast and image sharpness compared to conventional AR displays without occlusion, marking the world’s first realization of high-contrast, high-fidelity three-dimensional AR scenes free from background interference. * benchtop prototype : a small-scale experimental device built prior to commercialization to verify a system’s performance and operating principles ▲ Experimental results showing a holographic 3D image that occludes the real background and casts a shadow ■ Expected Impact This research is significant in that it realized a true form of AR in which virtual images optically interact with the real environment. The proposed technology enables virtual objects to selectively block real-world light and cast shadows, establishing itself as a next-generation display technology capable of delivering an AR experience that feels natural to human visual perception. Additionally, this achievement marks a departure from conventional hologram optimization methods that have primarily relied on software-based methods. By directly integrating a dynamically operating Fourier filter into the algorithmic framework, the research introduced a new paradigm in which physical hardware enhances algorithmic performance. Highlighting the potential of hardware-algorithm co-design, this technology is expected to find applications in next-generation immersive display systems. ■ Researchers' Remarks Prof. Jae-Hyeung Park, who supervised the research, stated, “This study demonstrates the potential for a new form of AR in which virtual images interact with light of the real environment,” adding, “We will continue to develop next-generation display technologies that provide more natural and immersive visual experiences through the convergence of optics and artificial intelligence.” ■ Researcher Career Path First author Woongseob Han is currently pursuing his Ph.D. in the ECE Department at SNU, where he continues his research on near-eye displays for AR/VR and next-generation three-dimensional display technologies. After graduation, he plans to work as an optical design engineer in the field of next-generation immersive displays at research institutes or companies in Korea and abroad. [Reference] - Paper Title/Journal : “Enhancing Realism in Holographic Augmented Reality Displays Through Occlusion Handling”, Laser & Photonics Reviews - DOI : https://doi.org/10.1002/lpor.202501052 [Contact] Prof. Jae-Hyeung Park, Three-Dimensional Optical Engineering Laboratory, Department of Electrical and Computer Engineering, Seoul National University / 02-880-1825 / jaehyeung@snu.ac.kr Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=57000 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

Authors: Professor Jong-Ho Lee, Professor Jae-Joon Kim, Ph.D. candidate Kyung Min Lee, Ph.D. candidate Hunhee Shin, Postdoctoral researcher Ryun-Han Koo, and Dr. Jinwoo Park, Department of Electrical and Computer Engineering A research team led by Professor Jong-Ho Lee from the Department of Electrical and Computer Engineering at Seoul National University has achieved the remarkable feat of having three papers accepted at IEEE IEDM (International Electron Devices Meeting) 2025, the world’s most prestigious conference in the field of semiconductors. The team proposed a new direction for next-generation AI and low-power semiconductor technologies, demonstrating comprehensive research capabilities that span materials, devices, and systems. The first paper presents the development of an HfZrO₂ ferroelectric capacitor (FeCAP) that simultaneously achieves world-leading remanent polarization and low-voltage operation by introducing an HfO₂–TiO₂–HfO₂ triple interlayer structure. The device enables a non-destructive read memory window at 0 V, opening new possibilities for ultra-low-power and neuromorphic hardware applications. The second paper introduces a breakdown-based physically unclonable function (MBD-PUF) utilizing commercial magnetic tunnel junction (MTJ) devices, which achieves both bit error-free stable security responses and complete concealment of the original key. The proposed MBD-PUF operates reliably even at high temperatures up to 125 °C and demonstrates strong resistance against machine learning-based modeling attacks, proving its potential as a practical next-generation hardware security solution. This research was conducted in collaboration with Prof. Jae-Joon Kim’s research team from the ECE Department. The third paper reports the world’s first implementation of a real-time mixed-gas discrimination system that integrates a self-cancellation circuit with gas sensors on a single chip. By combining two FET-type gas sensors with a subtraction circuit, the system internally cancels the effects of interfering gases, enabling real-time, selective detection of target gases without external signal processing. The research team demonstrated the technology on ultra-compact, ultra-low-power hardware by detecting H2S gas emitted during egg spoilage, achieving real-time freshness monitoring. Prof. Jong-Ho Lee stated, “An integrated research approach combining device physics, circuits, and systems was key to achieving these results,” adding, “This outcome demonstrates that the research team at Seoul National University’s College of Engineering is leading the development of core technologies for next-generation intelligent semiconductors.” Figure 1. Overview of High-Performance FeCAP. Paper Title: HZO FeCap with Ultra-High 2Pr = 133 μC/cm2, PZT-Level Ec (1.17MV/cm @ 6 nm), and CMWε = 9.6 @ 0 V by Adopting HfO2-TiO2-HfO2 Pseudomorphic Interlayer Figure 2. Overview of MTJ-based MBD-PUF. Paper Title: Concealable and Bit Error-Free Breakdown-Based Physical Unclonable Functions Using Magnetic Tunnel Junctions Figure 3: Overview of Mixed Gas Discrimination System. Paper Title: Innovative Mixed Gas Discrimination System Using Integrated Self-Cancellation Circuit Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56986 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

Three research teams from the Integrated Circuits and Systems Laboratory (ICSL) led by Professor Jaehyuck Choi received top honors at the 26th Korea Semiconductor Design Challenge. The team composed of researchers Jeongbeom Seo, Yuhwan Shin, Junseok Lee and Joohan Lee won the Presidential Award, while the teams of Munjae Chae, Seheon Jang, Seungjae Lee and Sarang Lee, and Jaeho Kim, Myeongho Han, Hyunjun Song and Seohyeon Kwak each received Corporate Special Awards sponsored by MathWorks Korea and SK hynix, respectively. Presidential Award: Ultra-low-power quadrature clock generation and distribution technology with jitter filtering and instantaneous toggling functionality for next-generation High Bandwidth Memory (HBM) semiconductor applications Corporate Special Award (MathWorks Korea): A 65fsrms-Jitter and-272dB-FoMjitter,N, Fractional-N Digital PLL with a Quantization–Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration Corporate Special Award (SK hynix): High-speed, command-aware hybrid voltage regulator with minimized voltage drop for next-generation HBM semiconductor applications Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56976 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

Professor Jongmo Seo has been awarded an honorary doctorate from Pázmány Péter Catholic University (PPKE) in Budapest, Hungary. From October 6 to 17, 2025, Prof. Seo visited Hungary to conduct joint research with the Faculty of Information Technology and Bionics (ITK) at PPKE as part of the Korea-Hungary Joint Research Program supported by the National Research Foundation of Korea (NRF). During his visit, he also delivered special lectures on AR/VR technologies and artificial retinal systems designed to overcome visual impairments. In addition, he finalized the signing of a Memorandum of Understanding (MOU) between Seoul National University’s College of Engineering and PPKE’s ITK to bolster academic collaboration. The honorary doctorate was conferred on October 15 during the 390th anniversary ceremony of PPKE, which was founded in 1635. Following the conferment, Prof. Seo delivered a commemorative lecture titled “Unveiling Hidden Realms: The Power of Science and Engineering in Medicine.” During the ceremony, Dean György Cserey of ITK at PPKE remarked that “the conferment recognizes Prof. Seo’s outstanding research achievements in the fields of artificial vision and neural engineering, as well as his significant contributions to human welfare through the integration of medicine and engineering.” Founded in 1635 by Catholic bishop Péter Pázmány, PPKE is one of Hungary’s leading higher education institutions, offering education and research across a wide range of disciplines including theology, law, information technology and biotechnology. In particular, PPKE’s ITK is recognized as a pioneer in interdisciplinary research that bridges life sciences and engineering. The faculty also shares academic roots with Semmelweis University, Hungary’s top medical university, and Eötvös Loránd University (ELTE). Prof. Seo expressed his hopes that “the collaboration between SNU and PPKE will further expand into international joint research in the fields of medical informatics and bioelectronic engineering,” adding that “this honorary doctorate will serve as an opportunity to foster deeper academic exchange between Korea and Hungary.” Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56971 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

The research team of Dam Yun and Sunghyuk Choi from the Electric Energy Conversion Lab (Advisor: Professor Jung-Ik Ha) in the Department of Electrical and Computer Engineering at Seoul National University has received the Best Poster Award at the ‘IEEE/PSMA PwrSoC 2025 – 9th International Workshop on Power Supply on Chip’. The research team presented a poster titled “Flying Capacitor Multi-Level Converter at Constant Resonant Frequency with Negative-Voltage-Blocking GaN Switch”, which focuses on low-voltage, high-current intermediate bus converter (IBC) technology for 48V power systems used in AI data centers. By applying a resonant flying capacitor multilevel (RFCML) converter that utilizes high-energy density capacitors, the team proposed a new approach that efficiently converts 48V to 12V while reducing peak inductor current, thereby achieving higher power density and efficiency compared to conventional methods Held biennially, IEEE/PSMA PwrSoC is the world’s leading international workshop in the field of integrated power conversion and power management technologies, serving as a forum where global experts from academia and industry gather to discuss the latest technological advancements. Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56938 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

▲ (From left) Prof. Chul-Ho Lee (corresponding author), Ph.D. Yeon Ho Kim (first author), Ph.D. candidate Jaeho Lee (co-author), and integrated M.S.–Ph.D. candidate Donghyun Lee (co-author) Seoul National University’s College of Engineering announced that the research team led by Professor Chul-Ho Lee of the Department of Electrical and Computer Engineering has comprehensively proposed development directions for “gate stack”*, a core technology in two-dimensional (2D) transistors, which are emerging as next-generation semiconductor devices. *gate stack: the structure that controls current flow in transistors, consisting of a dielectric and metal stacked on top of the conductive layer On September 11, the findings were published in Nature Electronics (Impact Factor 40.9), a leading international journal at the forefront of semiconductor technology. ■ Research Background Modern semiconductors rely predominantly on silicon-based CMOS (Complementary Metal-Oxide-Semiconductor) technology, which has driven improvements in device performance and degree of integration over the past several decades. However, at today’s ultra-fine process scales of just a few nanometers (nm), this approach is encountering physical limitations. As a promising alternative channel material, 2D semiconductors—composed of atomically thin layers yet still capable of maintaining excellent electrical properties—are gaining increasing attention. Major global semiconductor companies and research institutes—including Samsung, TSMC, Intel, and IMEC—have already incorporated plans into their technology roadmaps to adopt 2D semiconductor transistors as the next-generation alternative to silicon in the mid-2030s, launching large-scale R&D efforts. In this context, 2D semiconductors are no longer a technology of the distant future but are rapidly emerging as the next mainstream driver of the global semiconductor industry. Yet, one of the greatest obstacles to the commercialization of 2D semiconductors lies in gate stack process technology. The gate stack is a core structure of semiconductors that controls the flow of current, and its quality directly determines the performance and reliability of the device. However, directly applying conventional silicon transistor processes to 2D semiconductors leads to degraded dielectric* quality, interfacial defects, and current leakage. Developing new materials and processes to overcome these issues is considered the most critical challenge for the commercialization of 2D semiconductors. *dielectric : insulating layer that prevents the flow of electricity ■ Research Achievements In response, Prof. Chul-Ho Lee’s research team analyzed various gate stack formation methods and quantitatively compared them across key performance metrics, thereby outlining a roadmap for future technological development. First, the research team classified gate stack formation methods into five categories: △van der Waals (vdW) dielectric, △naturally oxidized dielectric, △crystalline dielectric transfer method (quasi-vdW), △high-κ dielectric formation using a seed layer (vdW-seeded), and △methods compatible with conventional processes (non-vdW-seeded). Each method was then evaluated against key performance metrics—including interface defects, oxide film thickness, leakage current, threshold voltage, and operating voltage—and compared against the targets set by the International Roadmap for Devices and Systems (IRDS). Through this process, the team established a systematic development roadmap that can serve as a reference for both academia and industry. The research team also highlighted the potential of gate stacks incorporating ferroelectric* materials to be scaled up to next-generation devices. For example, ferroelectric-based gate stacks could enable ultra-low-power logic, non-volatile memory, and in-memory computing. In addition, the team provided concrete guidelines for practical implementation, addressing essential factors such as BEOL (Back-End-of-Line) process compatibility, low-temperature deposition below 400°C, wafer-wide uniformity, and long-term reliability, thereby emphasizing real-world industrial applicability beyond purely theoretical discussions. *ferroelectric: a material that retains electric polarization even in the absence of an external electric field. It is used in applications such as the implementation of non-volatile memory. This study is significant in that it quantitatively compared the performance of 2D semiconductor gate stacks across multiple metrics and evaluated them against IRDS targets, thereby providing a blueprint for the development of next-generation semiconductors. In doing so, the researchers not only confirmed the feasibility of implementing ultra-low-power, high-performance transistors but also proposed concrete technological directions considering future 3D monolithic stacking and BEOL-compatible processes, marking an innovative achievement. Furthermore, the technologies presented in this research are expected to serve as core foundational technologies driving the development of next-generation ICT infrastructure, including AI semiconductors, ultra-low-power mobile chips, and ultra-high-density servers. ■ Researchers' Remarks Prof. Chul-Ho Lee stated, “The biggest obstacle to the commercialization of 2D transistors is the implementation of high-quality gate stacks. This study provides a standard blueprint to overcome that challenge, which has significant academic and industrial implications. Moving forward, we plan to actively expand research on actual device integration and commercialization through industry–academia collaboration.” ■ About the Research Team Prof. Chul-Ho Lee’s research team at Seoul National University is actively leading the international academic community in the field of 2D semiconductor devices, particularly in high-quality gate stack technology. The team goes beyond purely theoretical proposals, conducting comprehensive research that encompasses actual device fabrication and process integration. By taking the lead in addressing key challenges of next-generation semiconductors, the group has established itself as a central player driving the global trajectory of future semiconductor research. ■ Researcher Career Path The first author of this paper, Ph.D. Yeon Ho Kim, is currently working as a postdoctoral researcher in the ECE Department at SNU, with a focus on metal-semiconductor contact and gate stack-related research for 2D semiconductor-based transistors. Building on this achievement, he is expected to demonstrate both academic and industrial leadership in the field of next-generation 2D semiconductor integrated devices. This research was conducted with support from the Next Generation Intelligence Semiconductor Development Program and the Nano and Materials Technology Development Program (Future Technology Laboratory), both funded by the Ministry of Science and ICT. Graduate students involved in the study also received support from BK21 Four and the Graduate School of AI Semiconductor. Figure 1. Roadmap of CMOS logic technology development and the potential of angstrom-scale 2D transistors [Reference] Kim, Y.H., Lee, D., Huh, W. et al. Gate stack engineering of two-dimensional transistors. Nat Electron (2025). https://www.nature.com/articles/s41928-025-01448-5 [Contact] Ph.D. Yeon Ho Kim, Laboratory of Emerging Electronics & optoElectronics (Lab.EEE), Department of Electrical and Computer Engineering, Seoul National University / julianus95@snu.ac.kr Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=56869 Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...

On September 5, Professor Emeritus Wook-Hyun Kwon of Seoul National University delivered a congratulatory address at the 30th anniversary ceremony of the integration of the Department of Electrical and Computer Engineering, held at the College of Engineering Building 1./SNU ECE Marking its 30th anniversary of integration, Seoul National University’s Department of Electrical and Computer Engineering heard from its first chair after integration, Professor Emeritus Wook-Hyun Kwon, who emphasized, “Just as the ECE Department achieved integration, barriers between departments must be broken down to further strengthen the competitiveness of engineering research.” The 30th anniversary ceremony took place on September 5 at SNU’s College of Engineering Building 1. Back in 1995, the departments of Electrical Engineering, Electronics Engineering, and Control and Instrumentation Engineering were merged into a single unit under the name “Department of Electrical Engineering”, integrating curricula, academic systems and research activities. At the time, Professor Kwon, then with the Department of Control and Instrumentation Engineering, joined his colleagues—including the late Professor Song-Yeop Han and Professor Hong Shick Min—in spearheading a voluntary integration. They believed that unifying disciplines would enable larger-scale research and reduce redundancy in research and education, thus opening pathways to progress. The newly merged Department of Electrical Engineering was later named the “Department of Electrical and Computer Engineering” in 2012, facilitating interdisciplinary collaboration ever since. In an interview with Chosun Ilbo, Professor Kwon remarked, “Just as economies of scale create efficiencies, research must also expand in scale to enable convergence and enhance global competitiveness. Thirty years ago, the objective of the ECE Department’s integration was to broaden the scope of research and contribute to industrial development.” He added, “Engineering entails the responsibility of advancing industries to raise national competitiveness, and engineers must continue to highlight the importance of STEM in our country.” On September 5 afternoon, the 30th anniversary ceremony of the integration of the ECE Department was held at the College of Engineering Building 1./SNU ECE On the issue of the so-called “crisis in STEM education,” Professor Kwon cautioned, “Top students are disproportionately heading to medical and dental schools, narrowing the talent pool.” He reflected, “In the 1990s, engineering drove industrial growth, and at SNU it stood as the most sought-after discipline in STEM, with the highest entrance scores. However, after the IMF financial crisis, talented individuals increasingly gravitated toward more stable career paths. It is now up to us engineers to demonstrate, through our efforts and achievements, the extent to which engineering contributes to national development.” In his address, Professor Kwon also urged the university to address concerns of “talent outflow” at SNU. “When outsiders evaluate our department, they often point out that there are no ‘star professors,’” he said. “We must cultivate an atmosphere where such faculty can emerge, because when outstanding individuals stand out, they become role models and inspire others.” At the ceremony, commemorative plaques were presented to the late Professor Song-Yeop Han, Professor Hong Shick Min, and Professor Wook-Hyun Kwon for their contributions to the integration of the department. Alumni including Joo-Kwan Kim, CEO of Naver Shopping, and Kay Woo, CEO of MVL, were also in attendance. Source: https://www.chosun.com/national/national_general/2025/09/07/ZXFEXD7UKZCAHEDFFUUARLWOXY/ Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr...