▲ Professor Jong-Ho Lee, Dr. Ryun-Han Koo, and Ph.D. candidate Jonghyun Ko of the ECE Department at Seoul National University

Seoul National University’s College of Engineering announced that a research team led by Professor Jong-Ho Lee from the Department of Electrical and Computer Engineering has proposed the world’s first AI semiconductor technology that integrates the core functions of generative AI into a single ferroelectric memory–based device platform.

This technology is particularly significant as it represents the world’s first demonstration of integrating the two key functions required for generative AI implementation—random sampling and stable computation—within a single memory array. By leveraging the voltage-dependent characteristics of ferroelectric memory, the research team implemented both probabilistic sampling using random telegraph noise (RTN) and deterministic computation using nonvolatile multilevel conductance states on a unified platform.

The research findings were published in Nature Communications, one of the world’s leading international scientific journals.

Generative AI has recently expanded rapidly into diverse applications, including image generation, video synthesis, autonomous systems, and personalized content creation. However, implementing generative AI directly on semiconductor chips remains a major challenge. Conventional AI semiconductors are primarily optimized for stable deterministic operations such as classification and inference, whereas generative models additionally require probabilistic functions capable of drawing random samples from latent spaces.

As such, previous approaches have often separated probabilistic sampling and decoding across different devices or external software modules, leading to limitations such as increased chip area, wiring complexity, power consumption, and latency. In particular, integrating both functions within a single memory-based hardware platform while maintaining compatibility with conventional CMOS processes and scalability has remained a difficult challenge.

To overcome these limitations, the research team focused on the voltage-dependent characteristics of hafnium oxide–based ferroelectric memory. In high-voltage regions, strong RTN emerges, enabling probabilistic sampling behavior, whereas in low-voltage regions, RTN is suppressed, allowing stable vector–matrix multiplication (VMM) operations using nonvolatile multilevel conductance states. Based on this mechanism, the team proposed a strategy for simultaneously realizing both randomness and computational stability required for generative AI within a single memory array.

This technology is particularly significant in that it integrates the sampling and decoding functions—previously separated in generative AI hardware—into a single ferroelectric memory–based platform. Without requiring a separate external random number generation module, the same device can perform different functions depending on its operating regime, demonstrating the potential to simultaneously improve integration density and power efficiency in future generative AI semiconductors.

The research team experimentally validated the concept using a NOR-type ferroelectric memory array fabricated on a 6-inch wafer. After optimizing the latent vector distribution by adjusting voltage and sampling time, the team applied the system to a variational autoencoder (VAE) and conducted image-generation experiments using the CelebA facial image dataset. The results confirmed the ability to generate images reflecting diverse facial attributes, while circuit-level verification demonstrated stable generative performance even after approximately 100,000 repeated operations.

This study is meaningful in that it demonstrated that two functions long treated separately in generative AI hardware can be integrated within a single CMOS-compatible ferroelectric memory–based device platform. The technology presents promising opportunities for simultaneously improving area efficiency and power efficiency in future on-chip generative AI accelerators, neuromorphic systems, and low-power edge AI semiconductors.

Ferroelectric memory, in particular, offers strong potential for future scalability toward large-scale generative AI hardware systems thanks to its high compatibility with existing semiconductor fabrication processes. Moving forward, the research team plans to further advance the technology toward real-time generative AI hardware through improvements in sampling speed, parallelism, array scale, and peripheral circuit optimization.

Prof. Jong-Ho Lee, who led the study, stated, “One of the key challenges in generative AI hardware is simultaneously achieving random sampling and deterministic computation. This study is meaningful in that it showed how the voltage-dependent characteristics of ferroelectric memory can be utilized to realize both functions within a single device platform.”

The study’s co-first authors, Ryun-Han Koo and Jonghyun Ko, are currently conducting research in Prof. Jongho Lee’s group at Seoul National University’s Department of Electrical and Computer Engineering, focusing on memory semiconductors, hardware AI, and low-power neuromorphic systems.

▲ Figure 1. Overview of the proposed ferroelectric memory–based hardware VAE system.
The ferroelectric memory array simultaneously performs probabilistic latent-variable sampling using RTN and deterministic decoding based on VMM.

▲ Figure 2. Verification of noise control and image-generation performance in ferroelectric memory.
The RTN-based randomness of the memory device varies depending on the applied voltage and sampling time conditions, resulting in changes to the generated latent vector distribution and image quality. Under optimized conditions, the research team confirmed balanced image generation on the CelebA dataset.

[Reference]

• Paper/Journal : “CMOS compatible ferroelectric tunnel junctions integrate stochastic sampling and deterministic computing for image generation”, Nature Communications
• DOI: 10.1038/s41467-026-72969-6

Source: https://ece.snu.ac.kr/ece/news?md=v&bbsidx=57729

Translated by: Changhoon Kang, English Editor of the Department of Electrical and Computer Engineering, changhoon27@snu.ac.kr