대규모 회로 및 시스템 연구실
VLSI Lab
연구실 소개 및 연구분야
We design energy-efficient and high-performance deep learning hardware accelerators. We focus on making neural networks lighter to enable deep learning computation in energy-constrained embedded computing devices. We also invent various circuits with low-power and variation-aware characteristics.
최근 관심분야 및 주요 연구과제
Our main/current interests are
A. Neural Network-Friendly Hardware / Hardware-Friendly Neural Network
- Network Compression: Pruning, Quantization
- Efficient Sparse Matrix Handling in NN Hardware
- Variable-Precision Neural Network Hardware
- Multi-bit Neural Network with Bitwise Activation
B. Near-/In-Memory Neural Network Computing
- Resistive Memory Based Neural Network Hardware
- SRAM based Binary Neural Network Hardware
- Mapping Large Neural Network on Memory Arrays
- Minimizing the Overhead of Peripheral Circuits(ADC/DAC) for In-Memory DNN Computing
- Process-Variation tolerant In-Memory NN Computing
- Near-Memory NN Processing in 3D High Bandwidth Memory (HBM)
- Spin Device based Neural Network Hardware
A. Neural Network-Friendly Hardware / Hardware-Friendly Neural Network
- Network Compression: Pruning, Quantization
- Efficient Sparse Matrix Handling in NN Hardware
- Variable-Precision Neural Network Hardware
- Multi-bit Neural Network with Bitwise Activation
B. Near-/In-Memory Neural Network Computing
- Resistive Memory Based Neural Network Hardware
- SRAM based Binary Neural Network Hardware
- Mapping Large Neural Network on Memory Arrays
- Minimizing the Overhead of Peripheral Circuits(ADC/DAC) for In-Memory DNN Computing
- Process-Variation tolerant In-Memory NN Computing
- Near-Memory NN Processing in 3D High Bandwidth Memory (HBM)
- Spin Device based Neural Network Hardware
