814.Transistor Scaling: History, Challenges, and Recent Research Trends

¾연사: 김라성 (Intel Corporation)

¾일시: 2017년 4월 27일(목) 오후 5:00~6:00

¾장소: 서울대학교 제1공학관(301동) 118호

Abstract:

The goal of this presentation is to give an introductory overview of the history of transistor scaling, challenges of modern nanoscale transistors, and recent research efforts to deliver novel switching devices. First, we briefly review the history of transistor scaling (“Moore’s law”) that has successfully enabled the integrated circuit (IC) technology for past 50 years. Silicon MOSFET (metal-oxide-semiconductor field-effect transistor) technology, however, is now approaching its scaling limit due to the manufacturing cost and fundamental physics. There are a lot of research activities going on to continue to deliver good switching devices in extremely scaled dimensions, and we will review some of highlights in this presentation. It is first clarified what are required of a good switching device (for OFF- and ON-state characteristics), and the key principles of different research approaches (novel device structures, novel materials, and novel physics) will be discussed focusing on how each approach tackles the scaling issue to realize a good switching performance.

Biography:

l 학력

2011   Purdue University, Electrical and Computer Engineering, PhD

2005   Seoul National University, Electrical Engineering and Computer Science, MS

2003   Seoul National University, Electrical Engineering, BS

l 경력

2011~current   Process TD Engineer

   Components Research, Technology and Manufacturing Group, Intel Corporation