컴퓨터이용설계 연구실
Computer-Aided Design Lab.
연구실 소개 및 연구분야
본 연구실의 연구 분야는 시스템 합성 설계에서 부터 physical 합성까지 모두를 카바하며, 특히 시스템-온-칩 설계 경향과, 임베디드 시스템 설계의 보편화에 따른 설계 변화 (예: 저전력)에 맞는 합성 기법 연구에 역점을 두고 있으며, 하드웨어 설계 뿐만 아니라 운영체제, 컴파일러, 하드웨어/소프트웨어 Co-design 영역까지 모두 카바한다. 그러나, 특히 뿌리를 두고 있는 분야는 아키텍쳐 설계 영역이며, 모든 설계 과정에서의 중심에 있다.
최근 관심분야 및 주요 연구과제
- 3D-IC Design
- Reliable and Variation-Aware Synthesis
- Thermal-aware Soc Design
- Embedded System Design
- Architecture-level Synthesis for System-on-Chip design
- Logic-level Synthesis
- High-level Synthesis
- Reliable and Variation-Aware Synthesis
- Thermal-aware Soc Design
- Embedded System Design
- Architecture-level Synthesis for System-on-Chip design
- Logic-level Synthesis
- High-level Synthesis
주요 논문/특허
[1] Heechun Park and Taewhan Kim, "Synthesis of TSV Fault-Tolerant 3D Clock Trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 2, pp. 266-279, February 2015.
[2] Minseok Kang and Taewhan Kim, "Integrated Resource Allocation and Binding in Clock Mesh Synthesis," ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 30:1-30:28, June 2014.
[3] Sangdo Park and Taewhan Kim, "Edge Layer Embedding Algorithm for Mitigation On-Package Variation in 3D Clock Tree Synthesis," Integration, the VLSI Journal, Vol. 47, No. 4, pp. 476-486, September 2014.
[4] Byunghyun Lee and Taewhan Kim, "Algorithms for TSV Resource Sharing and Optimization in Designing 3D Stacked ICs," Integration, the VLSI Journal, Vol. 47, No. 2, pp. 184-194, March 2014.
[5] Deokjin Joo and Taewhan Kim, "A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems,", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014.
[6] Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim, "An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013.
[7] Tak-Yung Kim and Taewhan Kim, "Resource Allocation and Design Techniques of Pre-bond Testable 3D Clock Tree," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 138-151, January 2013.
[8] Jongyoon Jung and Taewhan Kim, "Statistical Viability Analysis for Detecting False Paths under Delay Variation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 111-123, January 2013.
[9] Deokjin Joo, Minseok Kang, and Taewhan Kim, "Design Methodologies for Reliable Clock Networks," Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012.
[10] Hyungjung Seo, Jaewon Seo, and Taewhan Kim, "Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling," The Computer Journal, Vol. 55, No. 11, pp. 1367-1382, November 2012.
[2] Minseok Kang and Taewhan Kim, "Integrated Resource Allocation and Binding in Clock Mesh Synthesis," ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 3, pp. 30:1-30:28, June 2014.
[3] Sangdo Park and Taewhan Kim, "Edge Layer Embedding Algorithm for Mitigation On-Package Variation in 3D Clock Tree Synthesis," Integration, the VLSI Journal, Vol. 47, No. 4, pp. 476-486, September 2014.
[4] Byunghyun Lee and Taewhan Kim, "Algorithms for TSV Resource Sharing and Optimization in Designing 3D Stacked ICs," Integration, the VLSI Journal, Vol. 47, No. 2, pp. 184-194, March 2014.
[5] Deokjin Joo and Taewhan Kim, "A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems,", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33, No. 3, pp. 423-436, March 2014.
[6] Kyoung-Hwan Lim, Deokjin Joo, and Taewhan Kim, "An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 3, pp. 392-405, March 2013.
[7] Tak-Yung Kim and Taewhan Kim, "Resource Allocation and Design Techniques of Pre-bond Testable 3D Clock Tree," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 138-151, January 2013.
[8] Jongyoon Jung and Taewhan Kim, "Statistical Viability Analysis for Detecting False Paths under Delay Variation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 111-123, January 2013.
[9] Deokjin Joo, Minseok Kang, and Taewhan Kim, "Design Methodologies for Reliable Clock Networks," Journal of Computing Science and Engineering, Vol. 6, No. 4, pp. 257-266, December 2012.
[10] Hyungjung Seo, Jaewon Seo, and Taewhan Kim, "Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling," The Computer Journal, Vol. 55, No. 11, pp. 1367-1382, November 2012.
