반도체 소자 연구실
Device Research Lab.
연구실 소개 및 연구분야
본 Device Research Laboratory는 Logic 소자 및 메모리 소자를 비롯한 나노 스케일의 반도체 소자분야에서 파급 효과가 큰 연구 결과들을 도출하는 것을 목적으로 활발한 연구를 수행하고 있다. 차세대 FinFET 소자 특성 및 신뢰성 연구, DRAM cell 소자 연구와 Random Telegraph Noise (RTN) 현상 분석을 통하여 Logic 소자 및 메모리 소자의 특성 이해, 소자 신뢰성 분석 및 성능 향상을 추구하고 있다.
▶ 연구 분야
1. 반도체 소자연구 (FinFET, DRAM, Random Telegraph Noise)
2. Device modeling & characterization (AC/DC modeling, Device measurement & simulation)
▶ 연구 분야
1. 반도체 소자연구 (FinFET, DRAM, Random Telegraph Noise)
2. Device modeling & characterization (AC/DC modeling, Device measurement & simulation)
최근 관심분야 및 주요 연구과제
▶ 최근 관심분야
- FinFET – Reliability and characterization analysis and 3D simulation
- DRAM – Next generation DRAM device (BCAT, SRCAT) analysis/simulation
- Device/Circuit Noise - (Flicker, RTN, Thermal) Noise modeling/analysis
▶ 주요 연구과제
- 5 nm node 이하용 Nano-belt형 트랜지스터 설계 및 7 nm node 소자의 reliability 분석
- 20 nm 이하 급 DRAM 셀 트랜지스터의 VRT (Variable Retention Time) modeling
- FinFET – Reliability and characterization analysis and 3D simulation
- DRAM – Next generation DRAM device (BCAT, SRCAT) analysis/simulation
- Device/Circuit Noise - (Flicker, RTN, Thermal) Noise modeling/analysis
▶ 주요 연구과제
- 5 nm node 이하용 Nano-belt형 트랜지스터 설계 및 7 nm node 소자의 reliability 분석
- 20 nm 이하 급 DRAM 셀 트랜지스터의 VRT (Variable Retention Time) modeling
주요 논문/특허
[1] Sung-Won Yoo, Joonha Shin, Youngsoo Seo, Hyunsuk Kim, Sangbin Jeon, Hyunsoo Kim, Hyungcheol Shin, “Characterizing traps causing random telegraph noise during trap-assisted tunneling gate-induced drain leakage”, Solid-State Electronics, vol. 109, no.7, pp. 42-46, Jul. 2015.
[2] Hyunsoo Kim, Youngsoo Seo, and Hyungcheol Shin, "Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman’s Method", Journal of The Institute of Electronics and Information Engineers, Vol. 52, no.4, pp. 668-673, Apr. 2015.
[3] Duckseoung Kang, Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Dong Hua Li, Yuchul Hwang, and Hyungcheol Shin, “Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory”,IEEE Electron Device Letters, Vol. 35, no. 3, pp. 348-350, Mar. 2014.
[4] Quan Nguyen Gia, Sung-Won Yoo, Hyunseul Lee, Hyungcheol Shin, “Dependence on an oxide trap’s location of random telegraph noise (RTN) in GIDL current of n-MOSFET”, Solid-State Electronics, vol. 92, no. 2, pp. 20-23, Feb. 2014.
[5] Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Duck-Seoung Kang, Dong Hua Li, Yuchul Hwamg, and Hyungcheol Shin, “Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory,” IEEE Electron Device Letters, Vol. 35, No. 1, pp. 51-53, Jan. 2014.
[2] Hyunsoo Kim, Youngsoo Seo, and Hyungcheol Shin, "Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman’s Method", Journal of The Institute of Electronics and Information Engineers, Vol. 52, no.4, pp. 668-673, Apr. 2015.
[3] Duckseoung Kang, Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Dong Hua Li, Yuchul Hwang, and Hyungcheol Shin, “Probability Level Dependence of Failure Mechanisms in Sub-20 nm NAND Flash Memory”,IEEE Electron Device Letters, Vol. 35, no. 3, pp. 348-350, Mar. 2014.
[4] Quan Nguyen Gia, Sung-Won Yoo, Hyunseul Lee, Hyungcheol Shin, “Dependence on an oxide trap’s location of random telegraph noise (RTN) in GIDL current of n-MOSFET”, Solid-State Electronics, vol. 92, no. 2, pp. 20-23, Feb. 2014.
[5] Kyunghwan Lee, Myounggon Kang, Seongjun Seo, Duck-Seoung Kang, Dong Hua Li, Yuchul Hwamg, and Hyungcheol Shin, “Separation of Corner Component in TAT Mechanism in Retention Characteristics of Sub 20-nm NAND Flash Memory,” IEEE Electron Device Letters, Vol. 35, No. 1, pp. 51-53, Jan. 2014.
